Leadless chip carriers provide a high number of input and output connections between a chip and a corresponding substrate in a relatively small package. Leadless chip carriers generally consist of a package containing a sheet of ceramic, such as alumina, which forms a chip carrier or base onto which the chip is mounted. The chip carrier is then surface mounted, usually onto a larger printed circuit board (PCB) or other substrate, simply by placing the carrier on the PCB contact pads which mirror those of the chip carrier. An electrical and mechanical connection is then made by soldering the chip carrier to the larger substrate by reflow soldering. This solder connection is typically made using solder paste or bumping the bottom of the chip carrier with solder balls. Electrical connection paths within the leadless chip carrier allow the pads of the chip to be brought to external contact pads on the chip carrier.
The area required for attaching the chip to the substrate or printed circuit board may be reduced by eliminating the chip carrier package or the chip carrier itself, and simply mounting the chip or integrated circuit directly on the substrate. In this process, known as flip-chip technology, a bumped integrated circuit (IC) carries the pad arrangement on a major top surface which is turned upside down (flipped), allowing direct coupling between the pads of the IC and matching contacts on the main circuit board or chip carrier. This direct connection is facilitated by depositing solder or gold bumps on the IC input/output pads or terminals. The flipped bumped IC is otherwise referred to as a flip-chip. The flip-chip is then aligned to the pads on the major substrate and all connections are made simultaneously by reflowing the solder or gold bumps.
In order to protect the solder joint or gold bump interconnection between the flip-chip and the substrate from fatiguing during thermal cycling, and to environmentally protect the chip, a dielectric material is applied between the flip-chip and the substrate. The dielectric material is typically an epoxy resin with a coefficient of thermal expansion similar to that of the solder, to improve thermal fatigue life. The epoxy resin is typically applied around the perimeter of the flip-chip or by underfilling the chip from the back side of the substrate. During this process, excess epoxy can easily flow beyond the perimeter of the flip-chip or chip carrier onto unwanted areas of the substrate, causing numerous problems and stress variations on the system. Attempts have been made to regulate the unwanted flow of epoxy resin by stringently controlling the quantity of epoxy resin dispensed and also the process variables. Many modifications of epoxy resins have been made to customize the viscosity of the resin to the required application, with limited success.
Clearly, an improved method of applying underfill to chip carriers or flip-chips is needed which provides a simple and cost-effective solution to the problem of epoxy bleedout.